The present invention relates to semiconductor structures, and more particularly relates to a stacked semiconductor structure including a through electrode and a method for forming a through electrode in such a semiconductor structure.
Three-dimensional integration of semiconductor devices is an important technique to break though the barrier to improve the performance with two-dimensional scaling so far. Conventional integration schemes, however, have cost issues in this regard, and so three-dimensional integration is not currently widespread. One of these problems results from the cost required for the formation and the connection of conductors for vertical electrical connection. For future expanded use of the three-dimensional integration, a process for integration at low cost has to be developed.
Japanese Patent Application Publication Nos. 2011-159889 and 2014-57065 both disclose a semiconductor device of a multi-layered structure including a through silicon via (TSV). Methods for manufacturing the semiconductor devices disclosed in these documents, however, are to joint substrates (layers) each having a TSV formed therein beforehand to couple their TSVs, and so the number of processes to form and connect conductors for vertical electrical connection increases, meaning an increase in cost.